Abstract:

With the escalating demand of data-intensive applications such as artificial intelligence (AI) and high-performance computing (HPC), off-chip data transfer has become a critical bottleneck. To address this challenge, the data rate of wireline SerDes has surged beyond 200Gb/s. This presentation will delve into the evolving trends in wireline communication and explore state-of-the-art SerDes design techniques that are pushing the boundaries of data transfer rates.

​Abstract​

System-in-Package solutions, where multiple chiplets are integrated by 2.5D/3D package technologies, have become more and more popular. To be economically viable, they require carefully co-optimizing system demand and package technology as well as the interconnects that enable communication between chiplets. This forum talk covers advanced package technologies and new capabilities they enabled. Circuit techniques used for 2.5D and 3D stacking will be introduced, including mitigation of inter-symbol-interferences, cross-chiplet timing closure, shielding against crosstalks, and integrity of power delivery networks.

奇景光電徐正池 資深處長將與各位分享
「與EMC共存-以車載顯示晶片為例」
歡迎有興趣的師長同學一同參加~

Abstract

​Quantum computing devices are believed to solve computational problems that are infeasible for classical computers. As quantum technology advances, it becomes increasingly challenging to verify whether these devices behave correctly, particularly as they reach scales that rule out any classical simulation methods. This talk will cover verification in quantum computing through interactive protocols and formal methods. First, we will review the current state of research on interactively verifying whether quantum devices solve computational problems correctly, followed by applications of these interactive protocols. Then, we will explore approaches to verifying whether the descriptions of quantum algorithms behave as intended using techniques from formal methods.

​

臺大圖書館洪翠錨編審將與各位分享
「研究生不可不知的文獻搜尋方法」
歡迎有興趣的師長同學一同參加~

梁群健博士將與各位分享
「休閒園藝」
歡迎有興趣的師長同學一同參加~

大綱：

生成式人工智慧（AI）自2022年底引起廣泛關注以來，已經逐步成為日常生活的一部分。這類模型不僅在規模上年增數十倍，甚至數百倍，而且在架構上也從單一模型演化至多專家系統，展現出前所未有的多樣性和複雜性。隨著各行各業積極探索將生成式AI技術融入工作流程，資訊安全和系統可控性的問題日益受到重視。

然而，生成式AI技術的普及面臨著一個重大挑戰：高昂的部署成本。這一挑戰不僅限制了技術的廣泛應用，也成為了許多組織採用這類先進技術的障礙。對此，群聯公司推出了aiDAPTIV+方案，一項革命性的計劃，旨在通過利用NAND Flash技術擴充高帶寬記憶體（HBM），從根本上降低成本。這一策略不僅能夠提升系統性能，也使得生成式AI的部署成本大幅下降，從而推動技術的更廣泛應用。

The emergence of generative artificial intelligence (AI) at the end of 2022 marked a significant evolution, as these technologies increasingly integrate into daily human activities. The scale of generative models has been expanding annually at an exponential rate, with architecture advancements evolving from single-model frameworks to complex multi-expert systems. As industries across the board incorporate generative AI into their operational processes, concerns regarding information security and controllability have come to the forefront. However, the high deployment costs associated with generative AI technologies pose a significant barrier to widespread adoption. In response, Phison has introduced the aiDAPTIV+ initiative, a revolutionary approach that leverages NAND Flash to expand High Bandwidth Memory (HBM), thereby substantially reducing costs.

7/15週一下午2:00邀請IEEE Fellow陳彥光博士蒞臨專題演講，主題為:AI輔助的圖像處理器和編解碼器，地點於博理館201會議室，歡迎踴躍出席!!

報名請至:

https://forms.gle/ebD2NN1HbTMzLquu5

萬俊明導演將與各位分享
「臺灣草鴞與西拉雅鴞郎的旅程」
歡迎有興趣的師長同學一同參加~

北市消防局黃凱馡消防員將與各位分享
「火災與地震的應變」
歡迎有興趣的師長同學一同參加~

有球科技施懷勛創辦人將與各位分享

「台大電機到台灣職棒的Trial and Error」

歡迎有興趣的師長同學一同參加~

Abstract:

In recent years, the computing capability of the semiconductor chips is driven not only by the foundry process scaling to the most advanced nodes, but also by the advanced package that heterogeneously integrates chips made by their most competitive process.This growth of computing capability on the one hand enables AI algorithms to deliver their potential, on the other hand expedites novel algorithms to evolve and reach beyond human imagination.

One of the most important trends is to divide and win: using the chiplet approach.The SoC (System on Chip) approach used to put all functions, such as computing units (xPU), memory, logic, I/O, analog, power management etc, into one single chip and its foundry process using its IP.However as system complexity, cost, die size, and design cycle time approach the limits, integration of chiplet from various foundry processes by advanced package become the most cost effective way.In addition, advanced package allows topology of connection, memory integration, power integration into 2.5/3D and vertical, hence implement system that was not possible by single SoC alone.Today, many of the most advanced AI computing solutions are implemented by the chiplet approach, and are making differences in the cloud and edge computing and switching, and in many innovative AI enabled end devices.

Last but not least, power consumption requires for the AI computing becomes critical economically and environmentally for the human civilization as a whole.Advanced package integrates ever-efficient power delivery into the package and optimized at the system level, and allows ultra-low power optical chips be integrated into one single package.

演講內容簡介：

每天花了一整天的時間待在研究室，住處與學校兩點一線，睡前躺在床上還是擔心著自己的研究進度、或是明天meeting可能會面對的狀況，你的生活是這樣嗎？研究生生活並不容易，好好休息，才能走得更為安適與自在。本講座將從研究生可能面對的挑戰與壓力出發，思考可以如何在過程中「好好休息」，維持生活中的平衡並保持前進的動力。

踢可股份有限公司楊皓宇執行長將與各位分享

「AIx 死x 機器人」

歡迎有興趣的師長同學一同參加~

大綱：

台積公司為500個以上的客戶提供服務，生產超過10000 種不同產品，被廣泛地運用在各種終端市場，例如高效能運算、智慧型手機、物聯網、車用電子與消費性電子產品，不同的客戶產品代表的是不同的製造和設計支援。 過去三十幾年年來，台積公司，供應商，與我們的客戶形成一個大聯盟，不斷的創新，將各種想法付諸實現。講者將從TSMC晶片製造服務的現況出發，藉由元件模擬的角度，討論各種產品衍生的電路設計自動化需求，及其面對的挑戰及發展。也會針對高效能運算設計所需的模擬，探討在人工智慧和機器學習的幫助下，對於傳統電路模擬架構可能的突破。最後，在技術簡介之外，講者也會分享多年的職場經驗，鼓勵大家參與未來無限的可能。

大綱：

透過陳良基教授與王素梅老師的真實故事，探索憂鬱症的樣貌及其對當事人和家庭的影響。藉由兩位講者分享，了解憂鬱症的挑戰，及如何在支持和被支持的過程中共同成長，一同攜手掙脫流沙的桎梏。

演講大綱：

1. 機器視覺與人工智慧淺談

2. 人工智慧在野生動物的應用與挑戰

3. 奇景光電超低功耗開源人工智慧解決方案

講題大綱：

1.   Mixed-Signal Circuit

2.  全球半導體產品分類與應用佔比

3.  晶片上電路種類與用途

4.  類比電路簡介與有線傳輸介面介紹

5.  先進製程的設計挑戰

6.  ChatGPT的使用與影響

7.  職場經驗分享

Abstract:
Gate sizing in digital circuits is a computationally hard problem. A common heuristic is to greedily resize the gate with the best trade-off for the change in delay vs. the change in area or power, iteratively until it converges, or until a maximum number of iterations. This is relatively fast, but it is quite suboptimal.

The gate-sizing problem can be formulated using Lagrangian relaxation, a machine learning approach, where gates are resized per a local objective with Lagrangian multiplier weighted delay constraints. Then, these multipliers are upsized to reduce constraint violations. It iterates between these two phases until it converges.

This talk will overview some historical circuit gate-sizing techniques, then discuss what is used in commercial electronic design automation software, and the challenges to adopt Lagrangian relaxation based gate-sizing in an industrial design flow. Software techniques to speed it up and reduce memory will also be detailed.

​畢業後一頭栽進快閃記憶體的工程師，他的人生究竟有甚麼閃亮的發展？快閃記憶體究竟是彎道超車的一顆星，還是即將撞上貨車的隕石？此演講將分享閃存猴子在茫茫人生中的深刻體驗。

Abstract: 

Over the years, edge AI has made significant strides, transitioning from applications like photo classification and face detection to enhancing video and gaming picture quality. The advent of generative AI has further propelled innovation, revolutionizing our life experiences. However, due to intensive computational and memory requirements, current generative AI applications primarily rely on cloud infrastructure.

In this presentation, we aim to explore the emerging trend of shifting from a cloud-centric approach to a collaborative cloud-edge paradigm for generative AI technologies. We will delve into the multitude of opportunities and challenges that lie ahead when supporting generative AI on edge devices. This transformation entails a synergetic blend of technological advancements, enhancements in hardware architecture, and the reduction of computational complexities, ultimately enabling the realization of novel generative AI applications.

臺大電子所特聘研究講座-張懋中博士將與各位分享

「Future Systems-on-Chip for Full Spectrum Utilization from RF to Optics」

歡迎有興趣的師長同學一同參加~

前台積電研發處長-楊光磊博士將與各位分享

「半導體產業面面觀」

歡迎有興趣的師長同學一同參加~

演講大綱/摘要:

1. Introduction to Package
2. Micron Packaging Sites
3. Package Trend

國立中央大學 周景揚校長將與各位分享

「每個人都是一本小說」

歡迎有興趣的師長同學一同參加~

聯詠科技iVoT產品事業處 王裕閔 副處長將與各位分享

「Applications of Edge Intelligence Vision Device」

歡迎有興趣的師長同學一同參加~

大麥影像傳播工作室 麥覺明導演將與各位分享

「人生風景無限 一條路 走就對了」

歡迎有興趣的師長同學一同參加~

展碁國際 林佳璋總經理將與各位分享

「談新鮮人如何建構未來競爭力」

歡迎有興趣的師長同學一同參加~

Heterogeneous integration poses new challenges to electronic design automation (EDA) and packaging communities and demands innovative solutions that must be built together with tight-knit collaborations. One key outcome is the EDA-enabled benchmarking capability that provides quantified evaluation of manufacturing technologies under development using system-level design metrics of interest. We present two such examples, first on glass vs. silicon as the interposer material choices, and second on hybrid bonding vs. micro bumping as the die bonding options, both targeting system-level power, performance, area, and cost (PPAC) optimization. In addition, thermal, power delivery, and other reliability related metrics are calculated and compared. Lastly, we discuss various algorithms and methodologies developed to enable these EDA tools that are based on conventional and AI approaches.